Google’s ‘Frozen V2’ TPU hardwires SRAM onto silicon, ditching TSMC’s CoWoS packaging for Gemini

Morgan Stanley says Google is designing its next TPU, codenamed Frozen V2, for Gemini workloads.

The chip may integrate SRAM directly on-die, potentially eliminating the need for TSMC’s CoWoS advanced packaging.

That could reduce cost and complexity while improving efficiency for Google’s AI hardware stack.

The report says early production could start next year or in 2027, with a larger ramp expected in 2028.

Possible partner involvement, including Marvell, has been mentioned, but nothing is confirmed.