Intel Cracks The Encapsulation Wall Blocking Hyper-Large Chips, Pushing Advanced Packaging To 24x Reticle Size and Beyond

Intel says its Rio Rancho, New Mexico site has pushed advanced packaging beyond current size limits.

The company is developing hyper-large chip packages up to 240 mm by 240 mm, or 24x reticle size.

It is using EMIB- and Foveros-based designs to address data transfer, power delivery, yield, warpage, and cooling.

If successful, the work could enable denser chiplet systems for AI and other compute-heavy workloads while boosting U.S. packaging capacity.