TSMC SoIC 3D stacking roadmap outlines path from 6-micron pitches today to 4.5-micron in 2029 — Fujitsu's Monaka CPU to benefit from face-to-face chiplet stacking

TSMC says its SoIC 3D packaging roadmap will shrink interconnect pitch from 6 microns in 2025 to 4.5 microns by 2029.

The company is also broadening support for face-to-face and face-to-back stacking, improving density for multi-die designs.

These advances should enable faster, lower-power chiplet integration for AI and HPC processors with better bandwidth and latency.

Future customer designs, including Fujitsu’s Monaka CPU, are expected to benefit from the tighter 3D integration roadmap.