PCI Express roadmap: The path to 1TB/s with PCI 8.0, the challenges of integration, and beyond
Key summary
PCIe has been a core I/O technology since the early 2000s, evolving from the original PCI and replacing shared buses with point-to-point links.
The standard has evolved since its 2004 introduction, with each major revision roughly doubling per-lane bandwidth while keeping backward compatibility.
New major PCIe versions are typically introduced every three to four years, though there was a notable slip between PCIe 3.0 and 4.0.
Recent iterations are becoming harder to implement because of tighter manufacturing tolerances, materials choices, and the need for retimers; PCI‑SIG oversees the standards.
Lane rates progressed from 2.5 GT/s (PCIe 1.0) to 128 GT/s (PCIe 7.0), with intermediate steps (8, 16, 32, 64 GT/s) and changes in encoding/signaling (NRZ, PAM4, Flit Modes).