DORA: Dataflow-Instruction Orchestration Architecture for DNN Acceleration

Researchers introduced DORA, an instruction-based overlay architecture for DNN acceleration.

DORA combines a custom ISA, compiler flow, and dataflow-aware scheduling to run varied workloads efficiently.

A prototype on AMD Versal VCK190 achieved up to 5x higher throughput with low performance variation across models.

The approach improves adaptability, memory management, and parallelism on existing reconfigurable hardware.