Huawei targets 1.4 nm-class chips by 2031 with new performance-focused design plan

Huawei unveiled a new Tau Scaling strategy in Shanghai, saying it could reach 1.4 nm-class transistor density by 2031 without relying solely on smaller transistors.

The approach focuses on faster data movement, shorter interconnects, and system-level efficiency; the first related Kirin chips are expected this year.

Huawei said its LogicFolding method could extend to Ascend AI chips and clusters by 2030, but it offered no independent performance proof.

The roadmap underscores Huawei’s effort to advance chip performance despite US sanctions, with potential implications for China’s semiconductor self-reliance and AI competition.