JEDEC pushes DDR5 MRDIMM memory to 12,800 MT/s, a 45% jump over Gen1 as AI datacenters starve for bandwidth

JEDEC has published a new DDR5 multiplexed rank data buffer standard for MRDIMM modules.

A multiplexed rank registering clock driver standard is nearing publication, with Gen2 and Gen3 work also advancing.

The next MRDIMM designs are targeting up to 12,800 MT/s to deliver much higher memory bandwidth.

The goal is to reduce memory bottlenecks in AI and other data-heavy datacenters.